vts02_dey_lbist LI-BIST: A Low-Cost Self-Test Scheme for SoC Logic Cores and Interconnects

Abstract
For deep sub-micron system-on-chips (SoC), interconnects
are critical determinants of performance, reliability
and power.

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ats01-syntest A Flexible Logic BIST Scheme and Its Application to SoC Designs

1. Introduction
Built-In Self-Test for logic circuits or logic BIST is
gaining popularity as an effective solution for the test
cost, test quality, and test reuse problems. Logic BIST
implements most of ATE functions on chip so that the test
cost can be reduced through less test time, less tester
memory requirement, or even a cheaper tester. Logic
BIST applies a large number of test patterns so that more
defects, either modeled or un-modeled, can be detected. In
addition, logic BIST makes it easy to conduct the at-speed
test for detecting timing-related defects. Furthermore, a
BISTed core makes SoC testing easier and such a core
can be tested even after being integrated into a system.

2. Logic BIST Scheme

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When the fault coverage of pure logic BIST is low, one
can use topup ATPG as well as test points

3. Experimental Results
The result of applying the described logic BIST scheme to
a real chip design is shown in Table 1.